The present invention relates to an information processing apparatus and particularly to a buffer memory control apparatus which is optimum to access a buffer memory efficiently.
U.S. Pat. No. 4,332,010 discloses a mechanism for detecting and handling a cache synonym.
One of the problems in making access to a buffer memory is a problem of synonyms. The term "synonyms" means a plurality of blocks of logical address pages corresponding to one and the same physical address. This is because a logical address is used as an address to make access to a buffer memory, and one and the same real address is assigned to a plurality of different logical addresses through paging a main storage.
In order to make access to a buffer memory, three functional portions are required as follows. A first one is a translation lookaside buffer (hereinafter abbreviated to "TLB") for translating the logical address to be used for the access into a physical address, a second one is a buffer address array (hereinafter abbreviated to "BAA") for storing address tags of blocks within a buffer storage, and a third one is the buffer storage (hereinafter abbreviated to "BS") for storing data by blocks.
In order to make access to the thus arranged buffer memory at a high speed, there is a parallel access system in which the above three functional portions are actuated in parallel to each other with a given logical address.
FIG. 1 is a block diagram showing an intermediate stage prepared to explain the parallel access system according to the present invention.
The logical address of a logical address register 1 is divided into two groups of bit positions, one of which groups consists of the bit positions (0, 1), (0, 2), . . . (2, 2), and (2, 3) which are to be subject to address translation, while the other group consists of the bit positions (2, 4), (2, 5), . . . (3, 6), and (3, 7) which are not subject to address translation. A TLB 2 is composed of pairs of logical addresses and physical addresses, so that upon reception of the address bits (0, 1) through (2, 3) to be subject to address translation from the logical address register 1 on a line 11, the TLB 2 puts out a physical address corresponding to the input logical address.
A BAA 3 is a memory storing physical addresses of blocks of a BS 4 and constituted by four rows (row 0-row 3), each row being constituted by four groups numbered with an address of two bits (2, 2) and (2, 3). According to this expression, it is possible to divide an address (32 bits) into four bytes (each 8 bits) from its MSB so as to specify the position of each bit by a format of (byte, bit).
A comparator circuit 8 constituted by a plurality of comparators compares a physical address read out on lines 19 from the BAA 3 in response to the address input to the BAA 3 with a physical address obtained on a line 10 through address translation in the TLB 2, and upon detection of coincidence between both the physical addresses, the comparator circuit 8 makes a hit signal 18 be logic "1". Upon reception of this hit signal, a logical hit/decode circuit 5 checks the logical state of the output signal of the comparator circuit 8 and produces a row selection signal 15 which is in turn applied to a row selecting circuit 6.
If the hit signal by the group numbered with the address bits (2, 2) and (2, 3) (called a logical group) of the four groups is not made to be logic "1" but of the hit signal by any other group (called a synonym group) is made logic "1", the logical hit/decode circuit 5 makes a synonym hit signal 9 be logic "1". Upon reception of the synonym hit signal 9, a synonym control circuit 7 makes a synonym invalidation signal 17 be logic "1" so as to invalidate the valide bits of the synonym group by use of the row and group numbers.
The BS 4 is constituted by four rows, and arranged to be accessed through a line 12 with the address bits "(2, 2), . . . (3, 3)" to be subject to address translation through a line 12. In response to the row selection signal 15, the row selection circuit 6 selects one of the buffer row data 14 read out from the BS 4 and puts out a buffer data 16.
For example, U.S. Pat. No. 4,332,010 concerns such an apparatus of the kind as described above.
In the apparatus described above, however, there is a problem of in access speed due to a physical problem in the designing of a memory chip of the BAA 3. That is, the quantity of association of the BAA is a product of the number of sets or rows and the number of groups, for example, 4.times.4=16 in this example of FIG. 1. The data width required to a memory chip increases in proportion to the quantity of association and the memory cell reading current increases in proportion to the data width. The quantity of heat generation of the memory cell is therefore increased because it is given by a product of the current and voltage required for memory cell reading. In order to accommodate the quantity of heat generation of the memory cell within a certain range, there is a problem that it cannot but to minimize the reading current even if the access speed is reduced.